WP3: Testbed Hardware Design and Production

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WP3 focuses on developing a specialized hardware accelerator to efficiently execute AI/ML algorithms designed in WP2 for space missions. Using Electronic Design Automation (EDA) techniques, including High-Level Synthesis (HLS) and Hardware Description Languages (HDL, VHDL), the project will design and optimize accelerator architectures leveraging Field-Programmable Gate Arrays (FPGAs). Performance modeling techniques, such as the roofline model, will be applied to evaluate theoretical efficiency.

The outcome of WP3 is a high-performance, low-power accelerator tailored for in-flight AI/ML applications. Additionally, a flexible soft-GPU hardware accelerator will be developed, allowing updates and algorithm modifications even during a mission's lifespan. These innovations will enhance the adaptability and efficiency of AI-driven space systems while reducing development time and improving computational performance.